1. Field of the Invention
The present invention relates to circuit testing, and more specifically to integrated circuit testing using weighted test inputs.
2. Background Information
Complex integrated circuits fabricated on a single semiconductor chip contain thousands of circuit elements, both sequential and combinational. These circuit elements are physically inaccessible for discrete stand-alone testing. Because of the complexity of the internal interconnections and interdependencies between the circuit elements, a testing of the individual circuit elements as well as the overall device integrity has becomes increasingly time consuming as the number of circuit elements has increased.
Prior art testing of integrated circuits employs the modification of at least some of the circuit under-test sequential (or storage) elements to include a latch and a coupled switch (multiplexer), and the serial coupling of these latched sequential elements to form at least one shift register between a test input generator and an output capturing circuit. The latches are each controlled by a system clock. Each serial coupling of sequential elements is referred to as a scan chain or scan register. Each latched sequential element is referred to as a scan element or scan flip-flop. The test inputs from the test generator are scanned into the storage elements and test results are scanned out of the storage elements through the scan register.
Each sequential circuit element is additionally coupled to at least one combinational circuit element forming a combinational logic block. In order to test the functionality and performance of a combinational logic block, various combinations of test bits arc input to the combinational logic block from the coupled scan element, received through a scan register. Each scan element (except at the ends of the chain) transmit an input to or receive an output from another coupled scan element or alternatively the coupled logic block according to the state of an signal input to the coupled switch. One of the storage devices forms the end of the chain, and receives a scan input from the test input generator that may be provided from an input pin to the integrated circuit. Another one of the storage devices forms the other end of the chain and provides a scan output provided to the output capturing circuit that may be to an output pin of the integrated circuit. Once a proper test input has been shifted into a scan element, it is switched to exercise the combinational logic block by transmitting the input state to the combinational logic block which respond to the test data in their usual manner. The result is captured by the scan element, and transferred to the capturing circuit by the scan chain, when the scan element is switched into the scan chain shifting mode.
Prior art testing employs a random pattern test input generator to generate to each scan chain of the integrated circuit under-test (and consequently selectably to each combinational logic block) a deterministic test pattern of logic 1 logic 0 bits, wherein the likelihood of a logic 1 value and a logic 0 value is equally likely. Prior art testing furthermore employs a weighted random pattern test input generator to generate random bits with probability of logic value 1 different from 0.5.
On a production line basis, it is rarely practical to fully test each element of an integrated circuit. Instead, a circuit is conventionally tested to a given level of accuracy. A high level of accuracy generally requires a plural number of input test sets for each scan chain. These test sets include a varying deterministic input weight. A large number of circuit elements therefore requires a great number of test data that must be delivered to the integrated circuit under-test on a real-time basis to minimize test time, where a test length which is unnecessarily high is unacceptable. Furthermore, this large amount of real-time data requires an expensive test fixture.
The problem is to provide a large amount of weight sets to an on-die weighted random pattern generator in real time fashion in order to achieve extremely high fault coverage.